Professionally, I work as a silicon design engineer at AMD, with a focus on functional verification methodology and verification.
Over the preceeding 20+ years in the EDA industry, I’ve worked in product development, marketing, and management roles in the areas of hardware/software co-verification, transaction-level modeling, IP encapsulation and reuse, and Portable Test and Stimulus.
A key industry focus from 2014 to present has been standardization of the Accellera Portable Stimulus Standard. The Portable Stimulus Specification (PSS) is a model-based capture of test intent that enables automated generation of random scenario-level tests. While there are many potential applications for such tests, a key target is creation of software-driven SoC-level tests for verifying proper integration, performance, and power.
Much of my work has focused on early stange technologies, with an emphasis on helping users understand how best to incorporate these new technologies into their existing design and verification flows.
I have a deep personal interest in functional verification methodologies and techniques, and contribute to several open source projects in that domain.
I enjoy writing about the work I’m doing, and enjoy presenting at conferences. You can find a list of publications here.
I maintain a blog for my personal projects where I write about new things I’m exploring, and enhancements I’m making to the various side projects that I work on.
I always have at least one (and typically several) personal open-source project running. I love learning new things, and find that projects are the perfect way for me to learn. Given my interest in hardware/gateware and functional verification, my projects, unsurprisingly, focus on this space.